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Products & solutions

RTL Build & Signoff Design Solutions for Complex SoC

  

SoC design groups continue facing high pressure to innovate quickly and deliver consistently.


Through a unified database with different APIs, Defacto’s STAR enables a cost-effective SoC Build & Signoff design process which opens new SoC integration and design optimization capabilities before and after logic synthesis.

 

In summary, STAR helps to face challenges of moving to sophisticated RTL coding styles like with System Verilog

Manage into a unified design flow the RTL conciliation process with the variety of multi-domain design standards:

    • Power intent such as UPF
    • Timing constraints such as SDC
    • Physical design information such as LEF/DEF
    • Architectural design formats such as IPXACT
    • Design Libraries such as Liberty
    • etc.

Also STAR provides a full automation to generate ready for synthesis RTL files by considering physical, power, timing & DFT constraints.

 

 

 

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