We are hiring a VIE for Japan and California.
We are hiring a VIE

VIE - Application Engineer in California

Missions:

As part of the company development, we are looking for an VIE candidate to provide technical support to users of Defacto’s EDA solutions.

He/she will be involved in the full lifecycle of customers: First contact, evaluation and support with the opportunity to work with American Major Semiconductor companies directly with the best Semiconductor experts. thanks to sustainable collaborations with “Majors”, Defacto Technologies is at the center of the next generation products design; like smartphones or computer processors, IoT or even key components for artificial intelligence applications.

He/she will be working closely with the R&D team based in Grenoble and with the Field Application Engineers based in North America, Asia and Europe. 

 In a “start-up” mindset, and in a young and dynamic growing team with a strong team spirit, the new member integration is always easy and fast. You will be considered as fully part of the team from the first day. Your opinion and advices will have direct impact into our discussions and strategic decisions

A technical 2-3 months training session is planned before the start of the VIE mission. The goal of this training is to prepare the candidate on both the technical aspects and the customer context where he/she will be directly involved.

 

Monthly remuneration: 3645€ (Non-contractual allowance laid down by decree and order, whose amount may vary in particular depending on the changes to the reference scale, the location of the position and the cases for deductions set out in the texts)

Job Location: San Francisco, United States

From 01 April 2020 to 01 October 2021 (for 18 months) 

 

Profil:

With the objective to build a long-term collaboration, we are looking for somebody who is:

  • Motivated by challenges and customer satisfaction
  • Curious with a constant desire to learn
  • Bold and that want to make things progress
  • Autonomous with also a strong team spirit

 

In order to achieve this mission within the best conditions, the following skills are expected from the Engineer:

  • Good knowledge of the UNIX / Linux environment
  • Mastery of one or several scripting languages (Tcl, Python)
  • General knowledge of the HDL languages (Verilog, VHDL)
  • General understanding of chip design flow (synthesis, simulation, test pattern generation)
  • Technical English speaking

 

Company Description :

Defacto Technologies is an innovative chip design software SME based at Grenoble in France and in the Silicon Valley. The company develops and provides advanced tools for chip design. Defacto counts most of the TOP 15 semiconductor companies as customer and thanks to sustainable collaborations with “Majors”, Defacto Technologies is at the center of the next generation products design; like smartphones or computer processors, IoT or even key components for artificial intelligence applications.

Defacto allows its customers to reach their objectives, more and more ambitious, by reducing design cycles and also by optimizing design flows. It enables a faster time to market and a better PPA (Performance, Power, Area) optimization.

  

Link to Civiweb website: https://www.civiweb.com/FR/offre/137621.aspx?&xtmc=defacto&xtnp=1&xtcr=1

This email address is being protected from spambots. You need JavaScript enabled to view it.

With the objective to build a long-term collaboration, we are looking for somebody who is:

-          Motivated by challenges and customer satisfaction

-          Curious with a constant desire to learn

-          Bold and that want to make things progress

-          Autonomous with also a strong team spirit

 

In order to achieve this mission within the best conditions, the following skills are expected from the Engineer:

-          Good knowledge of the UNIX / Linux environment

-          Mastery of one or several scripting languages (Tcl, Python)

-          General knowledge of the HDL languages (Verilog, VHDL)

-          General understanding of chip design flow (synthesis, simulation, test pattern generation)

Technical English speaking is a key differentiator

VIE - Application Engineer in Japan (Tokyo)

Missions:

As part of the company development, we are looking for an VIE candidate to provide technical support to users of Defacto’s EDA solutions.

He/she will be involved in the full lifecycle of customers: First contact, evaluation and support with the opportunity to work with Japanese Major Semiconductor companies directly with the best Semiconductor experts. thanks to sustainable collaborations with “Majors”, Defacto Technologies is at the center of the next generation products design; like smartphones or computer processors, IoT or even key components for artificial intelligence applications.

He/she will be working closely with the R&D team based in Grenoble and with the Field Application Engineers based in North America, Asia and Europe. 

 In a “start-up” mindset, and in a young and dynamic growing team with a strong team spirit, the new member integration is always easy and fast. You will be considered as fully part of the team from the first day. Your opinion and advices will have direct impact into our discussions and strategic decisions

A technical 2-3 months training session is planned before the start of the VIE mission. The goal of this training is to prepare the candidate on both the technical aspects and the customer context where he/she will be directly involved.

 

Monthly remuneration: 3076€ (Non-contractual allowance laid down by decree and order, whose amount may vary in particular depending on the changes to the reference scale, the location of the position and the cases for deductions set out in the texts)

Job location: Tokyo, Japan

From 01 April 2020 to 01 October 2021 (for 18 months) 

 

Profil:

With the objective to build a long-term collaboration, we are looking for somebody who is:

  • Motivated by challenges and customer satisfaction
  • Curious with a constant desire to learn
  • Bold and that want to make things progress
  • Autonomous with also a strong team spirit

 

In order to achieve this mission within the best conditions, the following skills are expected from the Engineer:

  • Good knowledge of the UNIX / Linux environment
  • Mastery of one or several scripting languages (Tcl, Python)
  • General knowledge of the HDL languages (Verilog, VHDL)
  • General understanding of chip design flow (synthesis, simulation, test pattern generation)
  • Technical English speaking
  • Technical Japanese speaking in a key differentiator 

 

Company Description :

Defacto Technologies is an innovative chip design software SME based at Grenoble in France and in the Silicon Valley. The company develops and provides advanced tools for chip design. Defacto counts most of the TOP 15 semiconductor companies as customer and thanks to sustainable collaborations with “Majors”, Defacto Technologies is at the center of the next generation products design; like smartphones or computer processors, IoT or even key components for artificial intelligence applications.

Defacto allows its customers to reach their objectives, more and more ambitious, by reducing design cycles and also by optimizing design flows. It enables a faster time to market and a better PPA (Performance, Power, Area) optimization.

  

Link to Civiweb website: https://www.civiweb.com/FR/offre/137750.aspx?&xtmc=defacto&xtnp=1&xtcr=1

This email address is being protected from spambots. You need JavaScript enabled to view it.

With the objective to build a long-term collaboration, we are looking for somebody who is:

-          Motivated by challenges and customer satisfaction

-          Curious with a constant desire to learn

-          Bold and that want to make things progress

-          Autonomous with also a strong team spirit

 

In order to achieve this mission within the best conditions, the following skills are expected from the Engineer:

-          Good knowledge of the UNIX / Linux environment

-          Mastery of one or several scripting languages (Tcl, Python)

-          General knowledge of the HDL languages (Verilog, VHDL)

-          General understanding of chip design flow (synthesis, simulation, test pattern generation)

Technical English speaking is a key differentiator

Application Engineer

Job description

The successful candidate will provide technical support to users of Defacto’s design solutions in several applications: Smartphone, autonomous vehicle, etc. He/she will be working closely with the R&D team based in Grenoble and with the Field Application Engineers based in North America, Asia and Europe. 

 

Profile

Engineer with a Master degree with a minimum of 3 years of experience in the domain, and the following skills:

  • Practice of UNIX / Linux, using C-shell
  • Expertise in scripting: Tcl, Perl
  • Knowledge of digital circuit design: Verilog, VHDL
  • Knowledge of front-end tools: RTL synthesis, Design For Test, Simulation, Formal equivalence
  • Experience of EDA tools in the design flow of integrated circuits
  • Minimum of 3 years’ experience
  • Your English skills are very good
  • Self-reliance and work actively with members of the R & D team.

 Experience within a large semiconductor or an EDA company is a plus

 

Job location

  • Grenoble, France
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The successful candidate will provide technical support to users of Defacto’s design solutions in several applications: Smartphone, autonomous vehicle, etc. He/she will be working closely with the R&D team based in Grenoble and with the Field Application Engineers based in North America, Asia and Europe. 

EDA Software Engineer

Job description

We are opening a position for highly motivated software developer engineer to work as part of our development engineering team.

Your responsibility may cover different aspects of software development: architecture, graphical user interface, unit testing, bug fixing and performance optimization. You will also have to work with the test engineering team to ensure quality of our products.

Profile

  • You must possess an Engineering degree, Master or PhD of Electrical Engineering/Computer Science (or similar)
  • Knowledge in C/C++ (STL)
  • Experience in the EDA or semiconductor field is a plus
  • Knowledge in Tcl scripting language is a plus
  • Knowledge in Qt libraries would be a plus
  • User experience in versioning and revision control system (ie: svn, git) is appreciated
  • Linux OS


The candidate must have excellent communication (oral/written) in French and in English. He/she must be self-directed, proactive and team-oriented.



Job location

  • Grenoble, France
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