Defacto in few words

Build a full SoC with the best trade-off (Time to Market, Power, Performance, Area, IP Reuse, Engineering cost) 

RTL Build&Signoff Design Solutions for Complex SoCs

SoC design groups continue facing high pressure to innovate quickly and deliver consistently.

Through a unified database with different APIs, Defacto’s STAR enables a cost-effective SoC Build & Signoff process which opens new design optimization capabilities before and after logic synthesis.

During the design process of complex SoCs, STAR helps to:

• Face challenges of moving to sophisticated RTL coding styles like with System Verilog
• Manage into a unified design flow the RTL conciliation process with the variety of multi-domain design standards: 
  • Power intent such as UPF
  • Timing constraints such as SDC
  • Physical design information 
  • Architectural design formats such as IPXACT
  • Libraries
  • etc.
• Provide the automation to generate ready for synthesis RTL by considering physical, power, timing & DFT constraints

More Information

It’s now possible to access our DATE customer presentation

It’s now possible to access our DATE customer presentation using the following link: https://www.date-conference-virtual.com/online-program/session?s=4.8+#e166

ATOS is presenting how they built a Scalable NoC, SoC with associated Testbench generation using STAR

Summary:

As part of the Mont Blanc 2020, European scalable, modular and power efficient HPC processor, ATOS designs and implements a NoC which includes NoC Xpoints, Protocol agents and system cache.

Our Network on Chip (NoC) is based on basic Xpoint modules which are connected to each other to make a scalable NoC. Each Xpoint module has :

• 4 internal CHI Interface (1 per direction) where all the Xpoint modules are connected to
• 2 End Points CHI Interface which are the entry/exit points of IPs on the System on Chip (Soc)

A CHI interface contains 4 channels interfaces: Request, Data, Snoop and Response. Each channel is fully configurable in each direction and is implemented with Configurable System Verilog Interface. This makes a lot of parameters to handle as we plan to implement an 8x8 NoC which includes 64 Xpoint modules with corresponding parameters set accordingly.

Defacto STAR tool is used to efficiently:

• instantiate all the Xpoint modules with corresponding parameters
• connect all the channels with corresponding System Verilog Interface
• connect the Error, status and configuration interfaces
• connect Protocol Agent on End Point interface (internally)
• create NoC entity.

The main benefits to choose Defacto STAR is

• NoC configuration change and RTL generation in seconds
• No need to develop our own tools

NoC module will then be integrated at SoC level and connected to IPs delivered by Third-parties. We also use Defacto STAR tool to generate the SoC RTL and associated Testbench.