Build a full SoC with the best trade-off (Time to Market, Power, Performance, Area, IP Reuse, Engineering cost)
SoC design groups continue facing high pressure to innovate quickly and deliver consistently.
Through a unified database with different APIs, Defacto’s STAR enables a cost-effective SoC Build & Signoff process which opens new design optimization capabilities before and after logic synthesis.
During the design process of complex SoCs, STAR helps to:
It’s now possible to access our DATE customer presentation using the following link: https://www.date-conference-virtual.com/online-program/session?s=4.8+#e166
ATOS is presenting how they built a Scalable NoC, SoC with associated Testbench generation using STAR
As part of the Mont Blanc 2020, European scalable, modular and power efficient HPC processor, ATOS designs and implements a NoC which includes NoC Xpoints, Protocol agents and system cache.
Our Network on Chip (NoC) is based on basic Xpoint modules which are connected to each other to make a scalable NoC. Each Xpoint module has :
A CHI interface contains 4 channels interfaces: Request, Data, Snoop and Response. Each channel is fully configurable in each direction and is implemented with Configurable System Verilog Interface. This makes a lot of parameters to handle as we plan to implement an 8x8 NoC which includes 64 Xpoint modules with corresponding parameters set accordingly.
Defacto STAR tool is used to efficiently:
The main benefits to choose Defacto STAR is
NoC module will then be integrated at SoC level and connected to IPs delivered by Third-parties. We also use Defacto STAR tool to generate the SoC RTL and associated Testbench.
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