STAR RTL Design Checker helps RTL Designers and Design Managers to better contain the increasing complexity of the RTL code (Verilog, VHDL, System Verilog).
No need to re-write all the code …. that's the great benefit from Defacto solution”
DAC was a real success for Defacto and we would like to thank again everybody who crossed by our booth in particular the presenters of the customer testimonials.
But what did customers say at DAC? SOCIONEXT in Japan said that they are reducing area cost up to 10% by adopting Defacto’s restructuring solution and also that they got 50X runtime improvement in 2 months!
A Major Communication Company said that they can now automatically split at RTL entire chips in smaller hard macros using Defacto’s STAR. With Defacto solutions they accelerated a lot their custom tool development with multi development languages support!
If you missed one of the presentations below, just let us know by clicking on the following link:
- Defacto Team
Sanjay Gangal interviews Chouki Aktouf, President and CEO of Defacto Technologies at 2016 DAC. The main announcements are:
Check the video to have more details about these 3 announcements
(The Defacto Video is one of the most famous on EDACafé)
A Versatile Design Platform with Multi-Language APIs
By using the STAR platform designers can create, explore, modify, and verify RTL designs within the same design flow. This is an ideal platform for fast design prototyping as well as development of complete new applications in shortest possible time.
Read the full article on Semiwiki:
Defacto is creating series of videos about typical applications when using the Defacto's STAR solution.
Enjoy the following first videos !
Defacto introduces the RTL "Build&Signoff" design methodology. Based on a set of EDA tools that work seamlessly together, a user can build, explore, edit and verify RTL design within the same design flow.
The "Unified Design Flow" based on the STAR solution which helps build a design flow to jointly handle IPXACT, RTL, LEF/DEF & UPF languages with the related design tasks.
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