As the number of CPUs, GPUs, and IPs is growing in today’s SoCs, power management is becoming a very complex task, especially during the exploration phase where design restructuring is used in order to find the most optimal low power architecture, to meet the design requirements for performance, die size and power consumption.
Knowing the complexity of nowadays designs, a design needs to address a multitude of choices and questions: Why should I move a certain block? Where should I move it? Will there be an impact on timing closure or low power or both? How long will it take me to update the design? Etc...
Defacto is creating series of videos about typical applications when using the Defacto's STAR solution.
Enjoy the following first videos !
Defacto introduces the RTL "Build&Signoff" design methodology. Based on a set of EDA tools that work seamlessly together, a user can build, explore, edit and verify RTL design within the same design flow.
The "Unified Design Flow" based on the STAR solution which helps build a design flow to jointly handle IPXACT, RTL, LEF/DEF & UPF languages with the related design tasks.
STAR RTL Design Checker helps RTL Designers and Design Managers to better contain the increasing complexity of the RTL code (Verilog, VHDL, System Verilog).
Code Complexity Metrics (CCM) measure the level of complexity of an RTL code and help preventing synthesis and post-synthesis problems by pinpointing on critical areas of the code through the design hierarchy. For an RTL designer, Defacto CCM measures help flagging poorly written RTL code. For a Design Manager, such measures help estimating design effort given a new written RTL code.
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