Structural Verification & Signoff

STAR augments existing RTL verification flows by providing fully automated structural checks. Users can define and build their custom checks.

checker puzzle

 

High Level Benefits

Detect earlier the connectivity and testability issues

Monitor real time the IP integration process

Validate quickly 3rd party source IPs

Highlight complex and difficult to maintain RTL code

 

Typical Applications

RTL Simulation-Free Connectivity Checks

 

Pin-2-Pin tracing

  • Simulation-free connectivity checks under constraints
  • Ability to create custom checks

 

IP Validation - Design Centric Multi-View Checks

 

IP Validation

 

  • Quickly pinpoint inconsistencies
  • Intuitive power-intent schematics linked with std logic design schematics
  • Early validation of SDC against Design

IP DFT Signoff - Testability DRCs & Test Coverage Evaluation

 

IP DFT Signoff

 

  • Push-button flow for IP DFT Signoff
  • Autofix of Clocks and resets
  • Report testability weaknesses at RTL

 

 

RTL Code Complexity Metrics

 

Code Complexity Metrics

  • Complexity is correlated to higher bug count
  • Complex designs can hide unwanted behavior
  • More complex design is harder to Understand, Maintain, Test

 

Related Material 

Semiwiki: Analysis and Signoff for Restructuring

 

More Information

 

 

RTL Simulation-Free Connectivity Checks
Connection