Structural Verification & Signoff

STAR augments existing RTL verification flows by providing fully automated structural checks. Users can define and build their custom checks.

checker puzzle


High Level Benefits

Detect earlier the connectivity and testability issues

Monitor real time the IP integration process

Validate quickly 3rd party source IPs

Highlight complex and difficult to maintain RTL code


Typical Applications

RTL Simulation-Free Connectivity Checks


Pin-2-Pin tracing

  • Simulation-free connectivity checks under constraints
    • Constants propagation through logic gates and annotation in GUI
    • Cone extraction for custom load / driver extraction
    • Multiple filter options
  • Ability to create custom checks
    • Verification of memory pins connectivity
    • Verification of functional MUXing connectivity
    • Verification of clock gating enable




IP Validation - Design Centric Multi-View Checks


  • All checks are design centric
  • RTL or gate-level design description is the golden view
  • Library view is verified against design description
  • Supported format: SDC, UPF, LEF, LIB

IP Validation

Coherency Check

  • Quickly pinpoint inconsistencies
    • Syntax and parsing issues
    • Unmatched objects / commands
    • Quality checks (clocks, constraints on hierarchical pins)
  • Intuitive power-intent schematics linked with std logic design schematics
    • Hierarchical of flat power-intent representation
    • Power State Table visualization
  • Early validation of SDC against Design
    • Opportunity to fix Design or SDC

IP DFT Signoff - Testability DRCs & Test Coverage Evaluation


IP DFT Signoff


  • Push-button flow for IP DFT Signoff
    • By RTL designers before IP delivery
  • Autofix of Clocks and resets
  • Report testability weaknesses at RTL
    • Floating bus, unconstrained IO direction during test
    • Identification of flip-flops with possible clock and data race conditions

RTL Code Complexity Metrics


Code Complexity Metrics

  • Complexity is correlated to higher bug count
  • Complex designs can hide unwanted behavior
  • More complex design is harder to Understand, Maintain, Test

“Complexity is the worst enemy of security” 


Related Material 

Semiwiki: Analysis and Signoff for Restructuring


More Information



RTL Simulation-Free Connectivity Checks