RTL Build&Signoff Design Solutions for Complex SoCs

SoC design groups continue facing high pressure to innovate quickly and deliver consistently.

Through a unified database with different APIs, Defacto’s STAR enables a cost-effective SoC Build & Signoff process which opens new design optimization capabilities before and after logic synthesis.


During the design process of complex SoCs, STAR helps to:

  • Face challenges of moving to sophisticated RTL coding styles like with System Verilog
  • Manage into a unified design flow the RTL conciliation process with the variety of multi-domain design standards: 
    • Power intent such as UPF
    • Timing constraints such as SDC
    • Physical design formats such as LEF/DEF
    • Architectural design formats such as IPXACT
    • Library formats such as Liberty
  • Provide the automation to generate ready for synthesis RTL by considering physical, power, timing & DFT constraints

STAR Unified DataBase


More Information



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