Maintaining a continuous correlation between power intent (UPF and RTL) is a critical need for all ASIC design teams. Using STAR, the logic design hierarchy and power strategy are tightly linked to each other, so users can intuitively view and explore the mutual relationship. For example, any change of a UPF or an RTL code is automatically highlighted and reported by the tool.
Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical hierarchy appears in order to meet physical implementation constraints in the back-end of the design process...
For the devices we build today, design and implementation are unavoidably entangled. Design for low-power, test, reuse and optimized layout are no longer possible without taking implementation factors into account in design, and vice-versa. But design teams can’t afford to iterate indefinitely between these phases, so they increasingly adapt design to implementation either by fiat (design components and architecture are constructed to serve a range of implementation needs and implementation must work within those constraints) or through restructuring where design hierarchy is adjusted in a bridging step to best meet the needs of power, test, layout and other factors.
It is self-evident that large systems of any type would not be possible without hierarchical design. Decomposing a large system objective into subsystems, and subsystems of subsystems, has multiple benefits. Smaller subsystems can be more easily understood and better tested when built, robust 3rd party alternatives may be available for some subsystems, large systems can be partitioned among multiple design teams and complete system implementation can (in principle) be reduced to assembly of finished or nearly finished subsystems.
Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc) clean and synchronized with the RTL, to minimize iterations / schedule slips to the greatest extent possible in full-system verification and implementation - the true signoff steps.
Reaching Performance, Power and Area (PPA) targets is a very challenging problem for today’s SoC manufacturers, and one significant aspect of the challenge is the constant need for changing the design structure, sometimes significantly, to meet the aforementioned targets. Changing the design manually or using adhoc techniques can sometimes take weeks and it’s often error prone, causing schedule delays and unwanted verification effort. In this webinar we will present a new method for achieving RTL design restructuring quickly and efficiently, using the Defacto STAR platform, which relies on state of the art techniques and APIs to provide the users a multiformat, fully integrated, context aware and intuitive design environment.
A Versatile Design Platform with Multi-Language APIs
By using the STAR platform designers can create, explore, modify, and verify RTL designs within the same design flow. This is an ideal platform for fast design prototyping as well as development of complete new applications in shortest possible time.
Defacto presented this week in China, how security problems can be solved with the Defacto STAR tools
Grenoble, France, June 1st, 2015 --- Defacto Technologies S.A. today announced that Socionext Inc., a leading provider of System-on-Chip solutions, has adopted Defacto Technologies’ STAR RTL Design solution to provide unique RTL editing earlier in the design flow and very highly rapid gate-level design rearchitecturing, without requiring additional engineering resources.
“We often need RTL and gate-level design change in order to integrate them on SoCs. However those changes could be not convenient for logic designer while doing functional design and verification.” said Akihiro Yoshitake, General Manager, SoC Design Division at Socionext. “We found Defacto’s STAR has rich and unique feature of APIs to analyze and build design quickly without being intrusive logic designers work. We will take advantage of the STAR RTL Design solution into our complex SoC design flow.”
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