Reaching the Best Tradeoff for RTL SoC Design

To deliver greater functionality, higher performance, at much lower power for next-generation applications such as for automotive, mobile, and servers, leading edge SoCs are needed. Meeting time-to-market requirements and lowering the overall cost including design steps also become a critical factor of success.

Best Tradeoff

By adopting Defacto’s STAR design solutions, major semiconductor companies are continuously moving from traditional and painful post synthesis design tasks up to RTL. The ROI for such a move has been proven for tens of projects. 

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SoC Build & Signoff

SoC design groups continue facing high pressure to innovate quickly and deliver consistently.

Through a unified database with different APIs, Defacto’s STAR enables a cost-effective SoC Build & Signoff process which opens new design optimization capabilities before and after logic synthesis.

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Structural Verification with STAR


STAR provides a large set of structural verification capabilities at RTL. The provided checks are fully automated. On top of that, the user can build and run custom checks at RTL.


Typical Cases


Connectivity checking


Conciliate RTL with variety of multi-domain design standards

Thanks to its build and signoff capabilities and its unified database, STAR helps during the design process of complex SoCs to:

  • Face challenges of moving to sophisticated RTL coding styles like with System Verilog
  • Manage into a unified design flow the RTL conciliation process with the variety of multi-domain design standards: 
    • Power intent such as UPF
    • Timing constraints such as SDC
    • Physical design formats such as LEF/DEF
    • Architectural design formats such as IPXACT
    • Library formats such as Liberty
  • Provide the automation to generate ready for synthesis RTL by considering physical, power, timing & DFT constraints.


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RTL vs. UPF Coherency Checking using STAR


Maintaining a continuous correlation between power intent (UPF and RTL) is a critical need for all ASIC design teams. Using STAR, the logic design hierarchy and power strategy are tightly linked to each other, so users can intuitively view and explore the mutual relationship. For example, any change of a UPF or an RTL code is automatically highlighted and reported by the tool.



Defacto at DAC 2019 booth#667


Build a full SoC with the best trade-off (Time to Market, Power, Performance, Area, IP Reuse, Engineering cost) 


We were happy to announce the new benefits you can have based on success stories with our STAR Platform:

  • Reduce design cycles – From months to days
  • Detect earlier connectivity and testability issues
  • Save Area - Between 5 to 10%
  • Monitor real time the IP integration process
  • Reduce simulation time - Between 4 to 10X
  • Validate quickly 3rd party source IPs
  • Increase IP reuse ratio
  • Highlight complex and difficult to maintain RTL code

And don't miss our customer presentation "A unified design data consistency & coherency checking solution" - Tuesday June 4th at 2:00PM at the Defacto booth (#667)

Analysis and Signoff for Restructuring

For the devices we build today, design and implementation are unavoidably entangled. Design for low-power, test, reuse and optimized layout are no longer possible without taking implementation factors into account in design, and vice-versa. But design teams can’t afford to iterate indefinitely between these phases, so they increasingly adapt design to implementation either by fiat (design components and architecture are constructed to serve a range of implementation needs and implementation must work within those constraints) or through restructuring where design hierarchy is adjusted in a bridging step to best meet the needs of power, test, layout and other factors.


Defacto is drastically reducing simulation time for complex GPU chips

Grenoble, France, February 9th,

Defacto Technologies today announced that Synapse Design has tested STAR in collaboration with a major US based semiconductor company in the GPU market. Synapse Design used the RTL design restructuring capabilities of the Defacto’s STAR platform to generate clean and ready for synthesis RTL code.


“The semiconductor market is increasingly competitive particularly for end applications such as the GPU market that has stringent speed and time requirements. Synapse Design improved simulation time by 4x when using STAR in this well-known semiconductor company’s design flow,” said Marco Brambilla Associate Vice-President, Synapse Design. “In one case, thanks to STAR, we decreased simulation time from 54 hours to 10 hours under same conditions which is a huge breakthrough!”


“The collaboration with Synapse Design and their client who is a leader in GPU market, enhances and reinforces our capabilities in providing RTL design solutions to meet aggressive design time. Their tests showcase the uniqueness of STAR especially when it comes to complex designs in achieving significant time savings”, said Chouki Aktouf, Founder & CEO of Defacto Technologies. Mr. Aktouf added, “Synapse Design and their end client can now achieve an edge and competitiveness in the market with the added-value provided by the STAR platform”.


About Synapse Design



Design Deconstruction

It is self-evident that large systems of any type would not be possible without hierarchical design. Decomposing a large system objective into subsystems, and subsystems of subsystems, has multiple benefits. Smaller subsystems can be more easily understood and better tested when built, robust 3rd party alternatives may be available for some subsystems, large systems can be partitioned among multiple design teams and complete system implementation can (in principle) be reduced to assembly of finished or nearly finished subsystems.


Design Restructuring with STAR


Reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. Restructuring an SoC design by building multiple variants of the same SoC with different PPA scenarios, is often needed. STAR provides a complete and powerful automation platform to restructure complex SoCs at both RTL or gate-level.


Typical Cases



How RTL Design Restructuring Helps in Reaching PPA Requirements

Reaching Performance, Power and Area (PPA) targets is a very challenging problem for today’s SoC manufacturers, and one significant aspect of the challenge is the constant need for changing the design structure, sometimes significantly, to meet the aforementioned targets. Changing the design manually or using adhoc techniques can sometimes take weeks and it’s often error prone, causing schedule delays and unwanted verification effort. In this webinar we will present a new method for achieving RTL design restructuring quickly and efficiently, using the Defacto STAR platform, which relies on state of the art techniques and APIs to provide the users a multiformat, fully integrated, context aware and intuitive design environment.