STAR - RTL DFTRTL DFT enables DFT engineers and designers to check the DFT quality of a design at block, IP and chip levels before releasing the RTL to synthesis. With this EDA tool, the ATPG process starts earlier and delivers accurate test coverage results sooner. Beyond running both the DRC and the ATPG processes at RTL, this tool is also used for testability enhancement and DFT planning in compliance with mainstream DFT methodologies.
Typical RTL DFT features are :
For More Information :Additional STAR EDA Tools :Build custom and Language Independant Design Application at RTL with : |
Products & SolutionsLatest News![]() Defacto is drastically reducing simulation time for complex GPU chips![]() Structural Verification with STAR![]() Analysis and Signoff for Restructuring![]() Design Deconstruction![]() Joint poster session with Marvell Semiconductor at DAC![]() How RTL Design Restructuring Helps in Reaching PPA Requirements![]() RTL Correct by Construction |