SoC Integration & Design Restructuring

Reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. Restructuring an SoC design by building multiple variants of the same SoC with different PPA scenarios is often needed. STAR provides a complete and powerful automation platform to restructure complex SoCs.

Flow Design Restructuring and SoC Integration


High Level Benefits

 Reduce design cycles – From months to days

Save Area – Between 5 to 10%

Reduce simulation time – Between 4 to 10X

Increase IP reuse ratio


Typical Applications

Top Level Generation


Flow SoC Integration

  • IP Insertion
    • Early start
    • Ability to parameter instances
    • Ability to insert comments
    • Built-in Excel API
    • IPXACT support
  • Monitor SoC integration progress real-time
    • Report unconnected blocks/pins
    • Report clamped pins
    • Report overall connectivity status
  • Automated connectivity insertion
    • By naming convention
    • By configuration file (ie: xls)
    • Attribute/Interface based
    • Ability to clamp pins and to add glue logic


Design Restructuring



  • Split the top level in smaller hard macros
  • Maximize IP reuse
  • Layout density improvement
  • Power-Aware RTL Design Restructuring
  • Implement inter-block connections

Flow Design Restructuring Physical

 Flow Design Restructuring Power


 More details on Design Restructuring 


STAR Key Features 

  • Preserved look and feel for generated design
  • Ability to generate custom reports about design changes
    • Added / removed ports, nets, instances
    • Clusters connectivity before/after design restructuring
  • Unified data model
    • Multi-format support: Netlist, RTL, IPXACT, UPF, SDC, LEF/DEF
    • Automatic power intent / synthesis constraints refinement
    • Power aware design restructuring
  • Flexible insertion of feedthrough
  • Ability to clean/optimize logic for optimal synthesis
  • Unified API for design exploration and design editing


Related Material 

Semiwiki: Design Restructuring explained

Semiwiki: Another Application of Automated RTL Editing 

Semiwiki: Design Deconstruction

Design & Reuse / EDACafé: Defacto Technologies Announces Synapse Design in collaboration with a major semiconductor company Reduces Simulation Time by 5X When using Defacto's RTL Design Solutions


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