SoC Integration

Before synthesis, STAR enables full implementation capabilities towards IP and connectivity insertion with real-time integration progress monitoring.


 

High Level Benefits

 Reduce design cycles – From months to days

Increase IP reuse ratio

 

Key Features 

  • Multi-format IP Insertion
    • Multi-format support (RTL, Gate-level, IPXACT, UPF, SDC, LEF, DEF, Liberty, etc.)
    • Early start (even with partial design database)
    • Ability to parameter instances
    • Ability to insert comments
    • Ability to import power intent
  • Automated connectivity insertion
    • By naming convention
    • By configuration file (ie: xls)
    • Attribute/Interface based
    • Ability to clamp pins and to add glue logic
  • Monitor SoC integration progress real-time
    • Report unconnected blocks/pins
    • Report clamped pins
    • Report overall connectivity status
  • Generate full chip views based on specification file
    • IPXACT, UPF, RTL, Gate-level

  

More Information

 

 

Connection