Design Optimization

Reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. STAR helps optimizing large design netlists to reach aggressive PPA requirements, cost-effectively.

Layout density improvement towards area savings

Hierarchical manipulation based on floorplan changes

 

High Level Benefits

Save Area – Between 5 to 10%

Reduce design optimization runtime from days to hours

 

Key Features 

  • Layout density improvement
    • Reduce channels width in top level
    • Fix glue-logic at Top level
  • Optimize logic structures
  • Hierarchical manipulation (group, ungroup, move)
  • Automatic feedthrough insertion
  • Power/Physical -Aware Design Restructuring
  • UPF/SDC update
  • Ability to generate custom reports about design changes
    • Added / removed ports, nets, instances, etc.

  

More Information

 

 

Key Features

  • Preserved look and feel for generated RTL
  • Ability to generate custom reports about design changes
    • Added / removed ports, nets, instances
  • Flexible insertion of feedthrough

Benefits

  • Lower the burden on physical designers to reduce TAT (Turn Around Time)
  • Eliminate error-prone manual netlist editing, generate “correct-by-construction” netlists
  • Reduce die size and therefore cost, improve power consumption
  • Reduce project development schedule by several men-months
    • Manual design optimization can take weeks to several months for complex SoCs
    • With STAR, the same process can take just a few days, including the reviews
  • Unified naming convention for ECO phases
    • Avoid disturbance for physical design team
Connection