RTL Build&Signoff Design Solutions for Complex SoCs

SoC design groups continue facing high pressure to innovate quickly and consistently deliver.

In current design flows, RTL design is where most of the innovation is expected since it provides flexibility with a highest reusability potential.
Through a common and unified database with a full support of design languages including RTL, Defacto’s STAR enables the SoC build process fully at RTL.
Along with the Build process, STAR provides the RTL Signoff capabilities before moving to synthesis.

Build and Signoff - Unified Database SoC IntegrationStructural Checks   

During the design process of complex SoCs, STAR helps to:

  • Face challenges of moving to sophisticated RTL coding styles like with System Verilog
  • Manage into a unified design flow the RTL conciliation process with the variety of multi-domain design standards: 
    • Power intent such as UPF
    • Timing constraints such as SDC
    • Physical design formats such as LEF/DEF
    • Architectural design formats such as IPXACT
    • Library formats such as Liberty
  • Provide the automation to generate ready for synthesis RTL by considering physical, power, timing & DFT constraints

STAR Unified DataBase


More Information



RTL Simulation-Free Connectivity Checks