The STAR platform on Semiwiki

"getting to correct by construction RTL in modern design is not just about scripting the assembly, it’s also about being able to adapt the design as power and physical strategies change"


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EDA Senior Software Engineer

We are hiring !

Job Description:

As member of the Development team, you will develop and support Defacto RTL and Gate-level solutions. Your responsibilities as team member will include but not be limited to:

  • Participate in internal customer requirements collection,
  • Support and develop both existing and new solutions, 
  • Work with product and application engineers to harmonize/optimize the development environment and methodologies.


You must possess a Master degree or a PhD in Computer Science / Electrical Engineering with a minimum of 5 years of relevant experience in following areas: 

  • Software architecture (Object-Oriented) and development in EDA (Electronic Design Automation) 
  • C/C++, Tcl/Tk, CVS 
  • Linux OS
  • (Optional) VHDL, Verilog, SystemVerilog

The candidate must have excellent communication (oral/written) in French and in English, with very strong analytical skills. He/she must be self-directed, proactive and team-oriented.

Location: Grenoble, France 
Full/Part Time: Full Time 
Job Type: Experienced 
Regular/Temporary: Regular

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EDACafé DAC Interview

Sanjay Gangal interviews Chouki Aktouf, President and CEO of Defacto Technologies at 2016 DAC. The main announcements are:

  • Building and restructuring complex SoCs 
  • RTL Signoff about the coherency of the RTL with the other standards
  • Coverage of several APIs (Tcl, Perl, Java, Python)

Check the video to have more details about these 3 announcements

(The Defacto Video is one of the most famous on EDACafé)


Field Application Engineer (San Diego, CA)

We are hiring !

Job description

The successful candidate will provide technical support to users of  Defacto’s design solutions. He/she should be able to create and make persuasive technical presentations and conduct crisp, compelling demonstrations and benchmarks. Strong technical understanding of the product and the design environment will be critical.

Experience within a large semiconductor or an EDA company is a plus



  • Expertise in scripting: Tcl, Perl
  • Knowledge of digital circuit design: Verilog, VHDL
  • Knowledge of front-end tools: RTL synthesis, Design For Test, Simulation, Formal equivalence
  • Experience of EDA tools in the design flow of integrated circuits
  • Practice of UNIX / Linux, using C-shell
  • Minimum of 5 years experience
  • Your English is very good and professional
  • Self-reliance and work actively with members of the R & D team 

The candidate must have excellent communication (oral/written) in English.


Job location

  • San Diego CA, USA
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Defacto on Semiwiki

The RTL Build & Signoff platform is much enhanced for doing automated design partitioning and restructuring at the RTL level. 


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