RTL Correct by Construction

Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc) clean and synchronized with the RTL, to minimize iterations / schedule slips to the greatest extent possible in full-system verification and implementation - the true signoff steps.

 

A Versatile Design Platform with Multi-Language APIs

A Versatile Design Platform with Multi-Language APIs

 By using the STAR platform designers can create, explore, modify, and verify RTL designs within the same design flow. This is an ideal platform for fast design prototyping as well as development of complete new applications in shortest possible time.

 

Socionext Adopts Defacto Solution for RTL and Gate-level Design Analysis and Building

Socionext Adopts Defacto Solution

Grenoble, France, June 1st, 2015 --- Defacto Technologies S.A. today announced that Socionext Inc., a leading provider of System-on-Chip solutions, has adopted Defacto Technologies’ STAR RTL Design solution to provide unique RTL editing earlier in the design flow and very highly rapid gate-level design rearchitecturing, without requiring additional engineering resources. 

“We often need RTL and gate-level design change in order to integrate them on SoCs. However those changes could be not convenient for logic designer while doing functional design and verification.” said Akihiro Yoshitake, General Manager, SoC Design Division at Socionext. “We found Defacto’s STAR has rich and unique feature of APIs to analyze and build design quickly without being intrusive logic designers work. We will take advantage of the STAR RTL Design solution into our complex SoC design flow.”

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