STAR-DFT enables new verification capabilities at RTL for test setup and low power intent checking"
To improve DFT throughput and remove DFT bottlenecks, key DFT verifications need to be moved into the upstream design steps. Beyond running the DFT-DRC and ATPG process at RTL, STAR-DFT enables new verification capabilities at RTL for test setup and low power intent checking. Both DFT engineers and RTL designers have the ability to benefit from such a DFT flow.
Starting from RTL level, power intent and test setup can be validated in order to ensure that all power control signals (ie: retention control, isolation control, power-domain shutoff conditions) cannot be turned off during test process. With its unique capabilities to insert scan logic at RTL, STAR-DFT helps deciding about the scan architecture at RTL. Additional verification tasks such as power modes operation during scan test can be achieved pre-synthesis. The combination of STAR-DFT DRC engine with a full interoperability with mainstream ATPGs ensures that scan modes are valid for a given power configuration. For designs with multiple test modes, STAR-DFT allows incremental what-if analysis when the scan chain configuration is different for each power mode.
Join the Defacto team at ITC in Anaheim, October 6-8. And do not miss our presentation the October 6th at 12.00PM
