A Toolbox to Better Face Power-Aware DFT Challenges !

STAR-DFT enables new verification capabilities at RTL for test setup and low power intent checking"


To improve DFT throughput and remove DFT bottlenecks, key DFT verifications need to be moved into the upstream design steps. Beyond running the DFT-DRC and ATPG process at RTL, STAR-DFT enables new verification capabilities at RTL for test setup and low power intent checking. Both DFT engineers and RTL designers have the ability to benefit from such a DFT flow.

Starting from RTL level, power intent and test setup can be validated in order to ensure that all power control signals (ie: retention control, isolation control, power-domain shutoff conditions) cannot be turned off during test process. With its unique capabilities to insert scan logic at RTL, STAR-DFT helps deciding about the scan architecture at RTL. Additional verification tasks such as power modes operation during scan test can be achieved pre-synthesis. The combination of STAR-DFT DRC engine with a full interoperability with mainstream ATPGs ensures that scan modes are valid for a given power configuration. For designs with multiple test modes, STAR-DFT allows incremental what-if analysis when the scan chain configuration is different for each power mode.

Join the Defacto team at ITC in Anaheim, October 6-8. And do not miss our presentation the October 6th at 12.00PM


Socionext Adopts Defacto Solution for RTL and Gate-level Design Analysis and Building

Socionext Adopts Defacto Solution

Grenoble, France, June 1st, 2015 --- Defacto Technologies S.A. today announced that Socionext Inc., a leading provider of System-on-Chip solutions, has adopted Defacto Technologies’ STAR RTL Design solution to provide unique RTL editing earlier in the design flow and very highly rapid gate-level design rearchitecturing, without requiring additional engineering resources. 

“We often need RTL and gate-level design change in order to integrate them on SoCs. However those changes could be not convenient for logic designer while doing functional design and verification.” said Akihiro Yoshitake, General Manager, SoC Design Division at Socionext. “We found Defacto’s STAR has rich and unique feature of APIs to analyze and build design quickly without being intrusive logic designers work. We will take advantage of the STAR RTL Design solution into our complex SoC design flow.”


What customers say about DEFACTO ?

"当社では、適所にSTARを所有し、設計チームは毎日使用してます。単一のプラットフォームとして使用することを好みます。コマンド群を1セット学ぶだけで、ワン・ショットで作業することができます。時間の節約(IPの接続の為の作業日数と検証の為の作業週数)もできます。さらに、当社にとっての懸案事項も減らします。 何か問題が発生した場合に、その解決の為の適当な道具が入ったツール・ボックスを自分 のガレージに持っているようです。STARはホームデポのように、ユーザーが自分自身で必要とするアプリケーションを作成できるツールです。"