|
STAR Power | ||||
|
|
||
![]() |
||
|
Read RTL or gate-level and standard power formats (UPF) to define power architecture intent Detect power issues such as voltage level shifters properly inserted, power isolation logic is properly inserted and controlled Verify power management switches at RTL Edit and fix automatically power issues both at RTL and gate through effective insertion of low power structures (level shifters and isolation logic) Debug power issues at RTL through a graphical interface by cross probing RTL <--> schematic Generate reports: power-aware DRC violations, inserted logic for power fixing. |
||
Copyright © 2013 - DeFacTo Technologies