Whitepaper

Today, a typical design contains hundreds of clocks, several clock managers with frequencies coming from different design levels and locations. Structural clock verification early in the design flow is beneficial to shorten design cycles.

STAR-CK is a simulation-free tool which allows RTL DRC-based verification and debug of clock trees including clock connectivity and clock frequency per mode basis. It provides the flexibility to define as function or test modes, as necessary.

Typical STAR-CK features are:

Read RTL or gate-level

Source / destination clock path tracing under different test modes

DRC for path blockage, unexpected driver, period, waveform, ...

GUI debug of blocking points

Test bench generation with SVF support