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With the emerging design methodologies and design practice, testability sign-off is becoming more and more prevalent during RTL design. Even if DFT guidelines are considered by RTL designers in their day-to-day practice, it becomes critical to automate the testability sign-off process at RTL.
With the DeFacTo SIGNOFF solution, the RTL testability analysis, debug and enhancement are effective. DFT quality is strengthened at both RTL and gate by preserving current DFT implementation (scan, BIST, test compression, etc.) flow unchanged.
Compared to traditional flows and tools, SIGNOFF speeds-up test coverage enhancement process and enables new DFT verifications capabilities at both the block and the top levels.
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SIGNOFF help reaching higher DFT quality levels in a more predictable timeframe. It allows earlier DFT analysis & enhancement at the block, the IP core and the top levels and makes possible RTL DFT exploration including test compression, memory/logic BIST & JTAG. Also, a user can benefit from mainstream ATPGs before logic synthesis and have access to new RTL DFT verification capabilities such as RTL simulation under different test modes.
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