Solutions RTL to RTL Editing

Generic RTL to RTL Editing of Complex Designs

Traditionally, designers have used varied test structure insertion methods, from inserting structures manually at RTL, to inserting them post synthesis at gate level. They have also experimented with approaches which automate parts of the flow, but which are unaware of other flow constraints. Several problems are raised with such an approach such as, late design verification, error prone when designers intervene manually on gate-level netlists and potentially modifies timing paths, typically timing critical paths after synthesis. Inserting different structures at RTL avoids such problems, and most importantly helps in verifying complex IP cores and SoCs early in the design flow.

DeFacTo's RTL-to-RTL editing solution helps automating the integration process of complex structures, fully at RTL. This solution can be considered as a key part of several design flows and applications such as memory BIST, boundary scan and core based testing where different blocks and IP cores such as DFT structures and chip clock controllers, can be cost-effectively inserted at RTL.

Main Charactertics & Flow

Design Rule Checks (DRC) on RTL input

Comprehensive set of connection techniques

Powerful tracing signal mechanism across the design hierarchy

Easy development of custom Tcl applications

Related Tools

HiDFT-STAR

Key Benefits

Faster and error-free insertion of RTL structures

One software platform for several DFT applications