Solutions RTL DFT Verifications

Enabling New DFT Verifications at RTL

DFT closure at RTL becomes a major concern in modern design flows and design methodologies. It consists in detecting and solving DFT problems at RTL.

For internal scan which is the backbone of existing DFT methodologies and based on a patented technology, DeFacTo solution allows the insertion of internal scan logic at RTL. This makes new DFT verifications finally possible pre-synthesis by leaving the final scan implementation during or after logic synthesis.

With scan logic being available at RTL, new pre-synthesis DFT verifications such as RTL simulation of ATPG test vectors, analysis and management of test power at RTL, RTL verification of complex DFT architectures including scan, built-in self-test & boundary-scan become finally possible.

Main Characterics & Flow

Unique technology to insert scan logic at RTL

Hierarchical scan insertion using CTL models
Scan chains stitching based on existing data paths
Automatic integration at RTL of test compression blocks

Allows new DFT verifications at RTL

Generation of test bench for chain test
RTL simulation of ATPG test patterns
RTL test power analysis
RTL to RTL with DFT equivalence checking

Ensures interoperability with mainstream design flows & tools

Related Tools

HiDFT-SIGNOFF
HiDFT-STAR

Key Benefits

Speed-up simulation & test power analysis

"What-if" analysis of different DFT configurations

Identify earlier power-hungry blocks during test mode