Products HiDFT-SIGNOFF v3.0

Datasheet

Overview

HiDFT-SIGNOFF is the unique EDA tool that allows scan logic insertion at RTL. HiDFT-SIGNOFF permits designers to create a high-level design for test signoff methodology, closing the gap between RTL and DFT. HiDFT-SIGNOFF allows early identification of test issues and enables new pre-synthesis design and DFT verifications.

Key Features

Support for Verilog, VHDL or mixed designs

Enables testability signoff

Testability Design Rule Checking
Provides AutoFix capabilities for testability problems
ATPG-aware Test Coverage Evaluation
Pinpoints on testability (controllability / observability) weaknesses
Allows test point insertion for test coverage improvement

Unique technology to provide the capability to insert scan logic at RTL

Supports hierarchical scan insertion methodology using test models

Parsing and generation of Core Test Language (CTL) models

Allows new DFT verifications at RTL

Allows RTL simulation of ATPG test vectors and RTL test power analysis
Allows RTL to RTL with DFT equivalence checking

Ensures interoperability with mainstream design flows and tools