DeFacTo Technologies

	Newsroom Press Releases

	December 2009 EDA DesignLine : Bottlenecks removal in Design-For-Test flows for complex SoCs June 2009 EDA DesignLine : Tessolve evaluates DeFacTo RTL Testability Sign-off solution June 2009 Design&Reuse : DeFacTo demonstrates to Tessolve the effectiveness of its RTL testability sign-off solution June 2009 SOCcentral : Tessolve evaluates effectiveness of DeFacTo's RTL testability sign-off solution December 2007 Test & Measurement World : Increasing abstraction makes DFT more effective November 2007 Electronic Design : Design-for-Test tool eliminates need for gate-level scan October 2007 Test & Measurement World : DeFacTo unveils DFT product that eliminates need for gate-level scan October 2007 SCDsource : Startup lifts design for test to register-transfer level October 2007 EE TIMES : French startup brings Design-for-Test to a higher level October 2007 Design&Reuse : DeFacTo unveils industry's first high-level Design-for-Test sign-off methodology August 2007 Chip Design Magazine : Perform Design-for-Test and power management at the RTL April 2007 EDAcafe : Sequence teams with DeFacTo Technologies on DFT-Ready RTL power analysis