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Elimination of Bottlenecks in Typical Production Design For Test Flows
DFT is becoming crucial for the performance of System-on-Chip mass production and test cost. By introducing at-speed test and the integration of many heterogeneous design structures, DFT has never been so complicated, and it is becoming a bottleneck with traditional SoC design flows.
Using both HiDFT-SIGNOFF and HiDFT-STAR, a novel, an non intrusive and a realistic DFT flow with preliminary DFT insertion and verification capabilities at RTL, has been successfully considered as key components of a leading IDM production flow. This flow has demonstrated efficiency to discover DFT problems and enhance DFT quality much earlier than traditional DFT flows.
The overall benefits are a significant reduction of chip design cycles. As a result, the overall DFT throughput is drastically improved. First silicon which confirms the benefits of these novel flows has been successfully generated and validated.
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