RTL Design Checker enables complete access to the design database through queries that allow in-depth design exploration and GUI debugging tasks. The tool automatically and cost-effectively performs general purpose connectivity checks for a large number of pins simulation-free. Through the design hierarchy, this tool helps verify and debug multiple connections under different modes of operation within the same run.

STAR CCM helps RTL Designers and Design Managers to better contain the increasing complexity of the RTL code (Verilog, VHDL, System Verilog).

Code Complexity Metrics (CCM) measure the level of complexity of an RTL code and help preventing synthesis and post-synthesis problems by pinpointing on critical areas of the code through the design hierarchy. For an RTL designer, Defacto STAR - CCM measures help flagging poorly written RTL code. For a Design Manager, such measures help estimating design effort given a new written RTL code.


Typical STAR CCM features are :

  • Code complexity Score (McCabe Score)
  • Hardware Metrics
    • Ports
    • Nets
    • Parameters
    • Registers
    • Instances
    • Designs
  • Software Metrics
    • File paths
    • Number of (empty lines, design lines, comments lines)
    • Max conditional depth

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Additional STAR EDA Tools :

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