How RTL Design Restructuring Helps in Reaching PPA Requirements


Reaching Performance, Power and Area (PPA) targets is a very challenging problem for today’s SoC manufacturers, and one significant aspect of the challenge is the constant need for changing the design structure, sometimes significantly, to meet the aforementioned targets. Changing the design manually or using adhoc techniques can sometimes take weeks and it’s often error prone, causing schedule delays and unwanted verification effort. In this webinar we will present a new method for achieving RTL design restructuring quickly and efficiently, using the Defacto STAR platform, which relies on state of the art techniques and APIs to provide the users a multiformat, fully integrated, context aware and intuitive design environment.

Defacto in China for Security Applications

Defacto presented this week in China, how security problems can be solved with the Defacto STAR tools

Defacto presented typical applications around security such as:
  • Design For Testability & Security
  • Secure Sensitive Blocks/Ips/SoCs
  • Extraction of Design Metrics
  • From Spaghetti-like to Structured Designs
  • Non Regression Verification with Coherency Checking

RTL Correct by Construction

Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc) clean and synchronized with the RTL, to minimize iterations / schedule slips to the greatest extent possible in full-system verification and implementation - the true signoff steps.

 

Semiwiki Explains RTL Design Restructuring using Defacto

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical hierarchy appears in order to meet physical implementation constraints in the back-end of the design process...

 

A Versatile Design Platform with Multi-Language APIs

A Versatile Design Platform with Multi-Language APIs

 By using the STAR platform designers can create, explore, modify, and verify RTL designs within the same design flow. This is an ideal platform for fast design prototyping as well as development of complete new applications in shortest possible time.

 

Design Centric UPF Generation using STAR

Overview

Given a complex RTL design, the related UPF generation process is usually tedious and time consuming. 

STAR provides a user-friendly wizard to generate a correct-by-construction UPF code which is concise and readable. 

  

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