Don't miss our presentations at DAC !

Accelerate SoC Design Integration at RTL

Best-in class unified design flow for building an SoC at RTL will be covered. A full suite of basic and advanced SoC integration and RTL capabilities will be covered: top level generation from various sources (IP-XACT, RTL, gate-level), with a full support of HDL standards (SystemVerilog, Verilog and VHDL), padring integration, feed-through insertion, power aware design restructuring, etc.

 

Bring RTL Signoff to the next level

Detailed demos will be provided to cover a plenty of automatic checks fully at RTL: static checks for large number of connections through the hierarchy, RTL and UPF coherency, DFT signoff, etc.

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