Joint poster session with Marvell Semiconductor at DAC

Defacto and Marvell Semiconductor will be part of the poster session at DAC to present the success of a new methodology to integrate IPs and restructure RTL for large SoC designs.

Where: DAC Poster session

When: June, Monday 6th, 5:00 – 6:00 PM


With this new methodology of Defacto tool: STAR , Marvell was able to shorten the ramp-up time from first cluster design integration. Furthermore, the RTL code generation  process was accelerated significantly. Finally, the ratio of the RTL code reuse was augmented.

STAR is an RTL design platform that covers design restructuring, RTL signoff  and the RTL code generation needs. It replaces complex and hard to maintain in-house scripts and tools. AS an example and through basic and advanced editing capabilities, the platform shortens the path to synthesis-ready RTL code for complex IPs and SoCs.




  • Automated design editing at RTL or gate-level netlist using customized Tcl scripts
  • Integrated linting, DRC & GUI
  • Generation of custom reports

Supported formats

  • RTL : VHDL, Verilog, System Verilog, mixed designs
  • Gate-level netlist : Liberty, Verilog

Output design files

  • Synthesis-ready RTL which preserves indentation, comments, pre-compilation directives