What has been said about Defacto at DAC 2017?

Many of you crossed by our booth this year at DAC and we would like to again thank everybody we met. And thanks to Marvell for the joint presentation of our successful collaboration on SoC integration and design restructuring.

Sanjay Gangal from EDA Café interviewed Chouki Aktouf, President and CEO of Defacto Technologies at DAC 2017. The main announcements are:

  • RTL Restructuring to reach PPA requirements
  • Build highly complex SoCs even with partial design database
  • RTL Signoff on the coherency between RTL and other standards

Don't miss our presentations at DAC !

Accelerate SoC Design Integration at RTL

Best-in class unified design flow for building an SoC at RTL will be covered. A full suite of basic and advanced SoC integration and RTL capabilities will be covered: top level generation from various sources (IP-XACT, RTL, gate-level), with a full support of HDL standards (SystemVerilog, Verilog and VHDL), padring integration, feed-through insertion, power aware design restructuring, etc.

 

Bring RTL Signoff to the next level

Detailed demos will be provided to cover a plenty of automatic checks fully at RTL: static checks for large number of connections through the hierarchy, RTL and UPF coherency, DFT signoff, etc.

Semiwiki Explains RTL Design Restructuring using Defacto

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical hierarchy appears in order to meet physical implementation constraints in the back-end of the design process...

 

Joint poster session with Marvell Semiconductor at DAC

Defacto and Marvell Semiconductor will be part of the poster session at DAC to present the success of a new methodology to integrate IPs and restructure RTL for large SoC designs.

Where: DAC Poster session

When: June, Monday 6th, 5:00 – 6:00 PM

 

With this new methodology of Defacto tool: STAR , Marvell was able to shorten the ramp-up time from first cluster design integration. Furthermore, the RTL code generation  process was accelerated significantly. Finally, the ratio of the RTL code reuse was augmented.

STAR is an RTL design platform that covers design restructuring, RTL signoff  and the RTL code generation needs. It replaces complex and hard to maintain in-house scripts and tools. AS an example and through basic and advanced editing capabilities, the platform shortens the path to synthesis-ready RTL code for complex IPs and SoCs.

 

  

Features

  • Automated design editing at RTL or gate-level netlist using customized Tcl scripts
  • Integrated linting, DRC & GUI
  • Generation of custom reports

Supported formats

  • RTL : VHDL, Verilog, System Verilog, mixed designs
  • Gate-level netlist : Liberty, Verilog

Output design files

  • Synthesis-ready RTL which preserves indentation, comments, pre-compilation directives

Semiwiki interviews Chouki Aktouf (CEO)

What does Defacto do?
Defacto provides RTL design solutions which help users to build a unified design flow where different standards like RTL for design description, UPF for power intent, SDC for timing constraints, LEF/DEF for physical design information, are considered jointly

What are the challenges facing EDA companies today?
Main challenges are three fold, first, different mergers between major semiconductor companies.

Second challenges are the new opportunities around design solutions especially for killing apps like for automotive, IOT (Internet of Things) and the ability to provide compelling solutions.

Last but not least are the em...

 

How RTL Design Restructuring Helps in Reaching PPA Requirements


Reaching Performance, Power and Area (PPA) targets is a very challenging problem for today’s SoC manufacturers, and one significant aspect of the challenge is the constant need for changing the design structure, sometimes significantly, to meet the aforementioned targets. Changing the design manually or using adhoc techniques can sometimes take weeks and it’s often error prone, causing schedule delays and unwanted verification effort. In this webinar we will present a new method for achieving RTL design restructuring quickly and efficiently, using the Defacto STAR platform, which relies on state of the art techniques and APIs to provide the users a multiformat, fully integrated, context aware and intuitive design environment.

What did Defacto customers say at DAC in Austin?

No need to re-write all the code …. that's the great benefit from Defacto solution”

DAC was a real success for Defacto and we would like to thank again everybody who crossed by our booth in particular the presenters of the customer testimonials.

But what did customers say at DAC? SOCIONEXT in Japan said that they are reducing area cost up to 10% by adopting Defacto’s restructuring solution and also that they got 50X runtime improvement in 2 months!

A Major Communication Company said that they can now automatically split at RTL entire chips in smaller hard macros using Defacto’s STAR. With Defacto solutions they accelerated a lot their custom tool development with multi development languages support!

If you missed one of the presentations below, just let us know by clicking on the following link:

http://www.defactotech.com/contact-us

  • Generating a Layout friendly RTL/Netlist by Defacto STAR
  • A Cost-effective RTL Partitioning Methodology for Large SoC Designs
  • Accelerate SoC Design Integration with STAR
  • Benefit from STAR as a Multi-Language APIs Design Platform
  • Bring RTL Signoff to the next level with STAR

- Defacto Team

Visit us at DAC booth #1220

Defacto Technologies is excited to announce new releases of its STAR platform and share customer experience during DAC in Austin TX, June 18-22.


Please save the date and visit us at the booth #1220.

Do not hesitate to contact us to set a meeting (Click Here).

Defacto on EDA Café

Defacto at DAC: Top semiconductor companies are presenting at the Defacto booth how Defacto's STAR helps accelerating SoC design integration

 

 

Defacto in China for Security Applications

Defacto will provide in collaboration with a leading security lab a private seminar in Beijing, China in January 14th about RTL code complexity analysis for security applications.

 

Defacto will showcasing how the STAR platform can help for:
 
 
 
RTL code Analysis
  • Build Security score based on an automated extraction of design and code metrics
  • Mimic laser attacks through pin constraint propagation and analysis
  • Check access path to sensitive blocks in complex designs  

 

RTL code generation
  • Secure RTL code exchange through sophisticated RTL obfuscation techniques
  • Generate 100% secured RTL code: Verilog, VHDL and System Verilog
   

 

For more information on the Defacto’s RTL code complexity solutions, 

Minalogic Showcase: Spotlight on the French EDA Innovators

For the second year in a row, Minalogic will follow 7 SMEs in DAC Austin, the most important event in the world dedicated to microelectronic (EDA) from the June 5th to 9th in Austin Texas. This mission will be under the "Minalogic International Development Plan" supported by the Auvergne-Rhône-Alpes region.

Minalogic will help these companies to improve their visibility throught the Minalogic comunication network to better take advantage from the DAC. 

Minalogic will distribute flyers during the event to present the skills and knowledges of each.

 

Also, in partnership with AEPI and CEA-Leti, Minalogic will organise a meeting animated by James Hogan, founder of Cadence and will have several guest from the ecosystem:

  • Philippe Magarshack, President, Minalogic
  • Firas Mohamed, General Manager – Silvaco France
  • Chouki Aktouf, Founder & CEO, Defacto Technologies – representative of the EDA SME members of Minalogic
  • Thierry Collette, Vice President, Architecture, IC Design & Embedded Software Division, CEA

The event is free but please register in advance for the raffle/drawing following the panel

Time: (Tuesday) 4:00 pm - 6:00 CST

Location: DAC Show floor SI2 Pavillion #239

 

 

 

Subcategories

Connection