Defacto is drastically reducing simulation time for complex GPU chips

Grenoble, France, February 9th,

Defacto Technologies today announced that Synapse Design has tested STAR in collaboration with a major US based semiconductor company in the GPU market. Synapse Design used the RTL design restructuring capabilities of the Defacto’s STAR platform to generate clean and ready for synthesis RTL code.


“The semiconductor market is increasingly competitive particularly for end applications such as the GPU market that has stringent speed and time requirements. Synapse Design improved simulation time by 4x when using STAR in this well-known semiconductor company’s design flow,” said Marco Brambilla Associate Vice-President, Synapse Design. “In one case, thanks to STAR, we decreased simulation time from 54 hours to 10 hours under same conditions which is a huge breakthrough!”


“The collaboration with Synapse Design and their client who is a leader in GPU market, enhances and reinforces our capabilities in providing RTL design solutions to meet aggressive design time. Their tests showcase the uniqueness of STAR especially when it comes to complex designs in achieving significant time savings”, said Chouki Aktouf, Founder & CEO of Defacto Technologies. Mr. Aktouf added, “Synapse Design and their end client can now achieve an edge and competitiveness in the market with the added-value provided by the STAR platform”.


About Synapse Design



Structural Verification with STAR


STAR provides a large set of structural verification capabilities at RTL. The provided checks are fully automated. On top of that, the user can build and run custom checks at RTL.


Typical Cases


Connectivity checking


How RTL Design Restructuring Helps in Reaching PPA Requirements

Reaching Performance, Power and Area (PPA) targets is a very challenging problem for today’s SoC manufacturers, and one significant aspect of the challenge is the constant need for changing the design structure, sometimes significantly, to meet the aforementioned targets. Changing the design manually or using adhoc techniques can sometimes take weeks and it’s often error prone, causing schedule delays and unwanted verification effort. In this webinar we will present a new method for achieving RTL design restructuring quickly and efficiently, using the Defacto STAR platform, which relies on state of the art techniques and APIs to provide the users a multiformat, fully integrated, context aware and intuitive design environment.

RTL vs. UPF Coherency Checking using STAR


Maintaining a continuous correlation between power intent (UPF and RTL) is a critical need for all ASIC design teams. Using STAR, the logic design hierarchy and power strategy are tightly linked to each other, so users can intuitively view and explore the mutual relationship. For example, any change of a UPF or an RTL code is automatically highlighted and reported by the tool.



Defacto in China for Security Applications

Defacto presented this week in China, how security problems can be solved with the Defacto STAR tools

Defacto presented typical applications around security such as:
  • Design For Testability & Security
  • Secure Sensitive Blocks/Ips/SoCs
  • Extraction of Design Metrics
  • From Spaghetti-like to Structured Designs
  • Non Regression Verification with Coherency Checking

Analysis and Signoff for Restructuring

For the devices we build today, design and implementation are unavoidably entangled. Design for low-power, test, reuse and optimized layout are no longer possible without taking implementation factors into account in design, and vice-versa. But design teams can’t afford to iterate indefinitely between these phases, so they increasingly adapt design to implementation either by fiat (design components and architecture are constructed to serve a range of implementation needs and implementation must work within those constraints) or through restructuring where design hierarchy is adjusted in a bridging step to best meet the needs of power, test, layout and other factors.


Semiwiki Explains RTL Design Restructuring using Defacto

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical hierarchy appears in order to meet physical implementation constraints in the back-end of the design process...


Design Deconstruction

It is self-evident that large systems of any type would not be possible without hierarchical design. Decomposing a large system objective into subsystems, and subsystems of subsystems, has multiple benefits. Smaller subsystems can be more easily understood and better tested when built, robust 3rd party alternatives may be available for some subsystems, large systems can be partitioned among multiple design teams and complete system implementation can (in principle) be reduced to assembly of finished or nearly finished subsystems.


Design Centric UPF Generation using STAR


Given a complex RTL design, the related UPF generation process is usually tedious and time consuming. 

STAR provides a user-friendly wizard to generate a correct-by-construction UPF code which is concise and readable. 



Joint poster session with Marvell Semiconductor at DAC

Defacto and Marvell Semiconductor will be part of the poster session at DAC to present the success of a new methodology to integrate IPs and restructure RTL for large SoC designs.

Where: DAC Poster session

When: June, Monday 6th, 5:00 – 6:00 PM


With this new methodology of Defacto tool: STAR , Marvell was able to shorten the ramp-up time from first cluster design integration. Furthermore, the RTL code generation  process was accelerated significantly. Finally, the ratio of the RTL code reuse was augmented.

STAR is an RTL design platform that covers design restructuring, RTL signoff  and the RTL code generation needs. It replaces complex and hard to maintain in-house scripts and tools. AS an example and through basic and advanced editing capabilities, the platform shortens the path to synthesis-ready RTL code for complex IPs and SoCs.




  • Automated design editing at RTL or gate-level netlist using customized Tcl scripts
  • Integrated linting, DRC & GUI
  • Generation of custom reports

Supported formats

  • RTL : VHDL, Verilog, System Verilog, mixed designs
  • Gate-level netlist : Liberty, Verilog

Output design files

  • Synthesis-ready RTL which preserves indentation, comments, pre-compilation directives

RTL Correct by Construction

Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc) clean and synchronized with the RTL, to minimize iterations / schedule slips to the greatest extent possible in full-system verification and implementation - the true signoff steps.