Analysis and Signoff for Restructuring

For the devices we build today, design and implementation are unavoidably entangled. Design for low-power, test, reuse and optimized layout are no longer possible without taking implementation factors into account in design, and vice-versa. But design teams can’t afford to iterate indefinitely between these phases, so they increasingly adapt design to implementation either by fiat (design components and architecture are constructed to serve a range of implementation needs and implementation must work within those constraints) or through restructuring where design hierarchy is adjusted in a bridging step to best meet the needs of power, test, layout and other factors.


Design Deconstruction

It is self-evident that large systems of any type would not be possible without hierarchical design. Decomposing a large system objective into subsystems, and subsystems of subsystems, has multiple benefits. Smaller subsystems can be more easily understood and better tested when built, robust 3rd party alternatives may be available for some subsystems, large systems can be partitioned among multiple design teams and complete system implementation can (in principle) be reduced to assembly of finished or nearly finished subsystems.


Semiwiki interviews Chouki Aktouf (CEO)

What does Defacto do?
Defacto provides RTL design solutions which help users to build a unified design flow where different standards like RTL for design description, UPF for power intent, SDC for timing constraints, LEF/DEF for physical design information, are considered jointly

What are the challenges facing EDA companies today?
Main challenges are three fold, first, different mergers between major semiconductor companies.

Second challenges are the new opportunities around design solutions especially for killing apps like for automotive, IOT (Internet of Things) and the ability to provide compelling solutions.

Last but not least are the em...


What has been said about Defacto at DAC 2017?

Many of you crossed by our booth this year at DAC and we would like to again thank everybody we met. And thanks to Marvell for the joint presentation of our successful collaboration on SoC integration and design restructuring.

Sanjay Gangal from EDA Café interviewed Chouki Aktouf, President and CEO of Defacto Technologies at DAC 2017. The main announcements are:

  • RTL Restructuring to reach PPA requirements
  • Build highly complex SoCs even with partial design database
  • RTL Signoff on the coherency between RTL and other standards

RTL Correct by Construction

Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc) clean and synchronized with the RTL, to minimize iterations / schedule slips to the greatest extent possible in full-system verification and implementation - the true signoff steps.


Joint poster session with Marvell Semiconductor at DAC

Defacto and Marvell Semiconductor will be part of the poster session at DAC to present the success of a new methodology to integrate IPs and restructure RTL for large SoC designs.

Where: DAC Poster session

When: June, Monday 6th, 5:00 – 6:00 PM


With this new methodology of Defacto tool: STAR , Marvell was able to shorten the ramp-up time from first cluster design integration. Furthermore, the RTL code generation  process was accelerated significantly. Finally, the ratio of the RTL code reuse was augmented.

STAR is an RTL design platform that covers design restructuring, RTL signoff  and the RTL code generation needs. It replaces complex and hard to maintain in-house scripts and tools. AS an example and through basic and advanced editing capabilities, the platform shortens the path to synthesis-ready RTL code for complex IPs and SoCs.




  • Automated design editing at RTL or gate-level netlist using customized Tcl scripts
  • Integrated linting, DRC & GUI
  • Generation of custom reports

Supported formats

  • RTL : VHDL, Verilog, System Verilog, mixed designs
  • Gate-level netlist : Liberty, Verilog

Output design files

  • Synthesis-ready RTL which preserves indentation, comments, pre-compilation directives

A Versatile Design Platform with Multi-Language APIs

A Versatile Design Platform with Multi-Language APIs

 By using the STAR platform designers can create, explore, modify, and verify RTL designs within the same design flow. This is an ideal platform for fast design prototyping as well as development of complete new applications in shortest possible time.


How RTL Design Restructuring Helps in Reaching PPA Requirements

Reaching Performance, Power and Area (PPA) targets is a very challenging problem for today’s SoC manufacturers, and one significant aspect of the challenge is the constant need for changing the design structure, sometimes significantly, to meet the aforementioned targets. Changing the design manually or using adhoc techniques can sometimes take weeks and it’s often error prone, causing schedule delays and unwanted verification effort. In this webinar we will present a new method for achieving RTL design restructuring quickly and efficiently, using the Defacto STAR platform, which relies on state of the art techniques and APIs to provide the users a multiformat, fully integrated, context aware and intuitive design environment.

Socionext Adopts Defacto Solution for RTL and Gate-level Design Analysis and Building

Socionext Adopts Defacto Solution

Grenoble, France, June 1st, 2015 --- Defacto Technologies S.A. today announced that Socionext Inc., a leading provider of System-on-Chip solutions, has adopted Defacto Technologies’ STAR RTL Design solution to provide unique RTL editing earlier in the design flow and very highly rapid gate-level design rearchitecturing, without requiring additional engineering resources. 

“We often need RTL and gate-level design change in order to integrate them on SoCs. However those changes could be not convenient for logic designer while doing functional design and verification.” said Akihiro Yoshitake, General Manager, SoC Design Division at Socionext. “We found Defacto’s STAR has rich and unique feature of APIs to analyze and build design quickly without being intrusive logic designers work. We will take advantage of the STAR RTL Design solution into our complex SoC design flow.”


Semiwiki Explains RTL Design Restructuring using Defacto

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical hierarchy appears in order to meet physical implementation constraints in the back-end of the design process...