Visit us at DAC booth #1220

Defacto Technologies is excited to announce new releases of its STAR platform and share customer experience during DAC in Austin TX, June 18-22.

Please save the date and visit us at the booth #1220.

Do not hesitate to contact us to set a meeting (Click Here).

Defacto in China for Security Applications

Defacto will provide in collaboration with a leading security lab a private seminar in Beijing, China in January 14th about RTL code complexity analysis for security applications.


Defacto will showcasing how the STAR platform can help for:
RTL code Analysis
  • Build Security score based on an automated extraction of design and code metrics
  • Mimic laser attacks through pin constraint propagation and analysis
  • Check access path to sensitive blocks in complex designs  


RTL code generation
  • Secure RTL code exchange through sophisticated RTL obfuscation techniques
  • Generate 100% secured RTL code: Verilog, VHDL and System Verilog


For more information on the Defacto’s RTL code complexity solutions, 

Minalogic Showcase: Spotlight on the French EDA Innovators

For the second year in a row, Minalogic will follow 7 SMEs in DAC Austin, the most important event in the world dedicated to microelectronic (EDA) from the June 5th to 9th in Austin Texas. This mission will be under the "Minalogic International Development Plan" supported by the Auvergne-Rhône-Alpes region.

Minalogic will help these companies to improve their visibility throught the Minalogic comunication network to better take advantage from the DAC. 

Minalogic will distribute flyers during the event to present the skills and knowledges of each.


Also, in partnership with AEPI and CEA-Leti, Minalogic will organise a meeting animated by James Hogan, founder of Cadence and will have several guest from the ecosystem:

  • Philippe Magarshack, President, Minalogic
  • Firas Mohamed, General Manager – Silvaco France
  • Chouki Aktouf, Founder & CEO, Defacto Technologies – representative of the EDA SME members of Minalogic
  • Thierry Collette, Vice President, Architecture, IC Design & Embedded Software Division, CEA

The event is free but please register in advance for the raffle/drawing following the panel

Time: (Tuesday) 4:00 pm - 6:00 CST

Location: DAC Show floor SI2 Pavillion #239




Semiwiki Explains RTL Design Restructuring using Defacto

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical hierarchy appears in order to meet physical implementation constraints in the back-end of the design process...


Follow us on LinkedIn


The Defacto LinkedIn page traffic is growing with already more than 150 people following us.

Please follow us to stay up-to-date about the more advanced RTL design solutions including EDA tools and breakthrough technologies

Semiwiki interviews Chouki Aktouf (CEO)

What does Defacto do?
Defacto provides RTL design solutions which help users to build a unified design flow where different standards like RTL for design description, UPF for power intent, SDC for timing constraints, LEF/DEF for physical design information, are considered jointly

What are the challenges facing EDA companies today?
Main challenges are three fold, first, different mergers between major semiconductor companies.

Second challenges are the new opportunities around design solutions especially for killing apps like for automotive, IOT (Internet of Things) and the ability to provide compelling solutions.

Last but not least are the em...


Defacto was at ITC Fort Worth

With nowadays System on Chips and the emerging market segments such for Automotive, Testability and safety requirements are more and more challenging for the design community. Designing complex DFT architectures after synthesis is no longer possible.


This year, Defacto will be demonstrating the first platform which helps exploring complex DFT architectures when combining different DFT methodologies:

  • Test compression
  • Scan
  • Memory planning (MBIST)
  • Etc.


Defacto team will be showcasing an advanced automated design solution for Early DFT Exploration and Planning. Please visit us at the Fort Worth TX Convention Center, booth #403. An in-depth technical presentation is provided on November 15 at 1.40PM .


What did Defacto customers say at DAC in Austin?

No need to re-write all the code …. that's the great benefit from Defacto solution”

DAC was a real success for Defacto and we would like to thank again everybody who crossed by our booth in particular the presenters of the customer testimonials.

But what did customers say at DAC? SOCIONEXT in Japan said that they are reducing area cost up to 10% by adopting Defacto’s restructuring solution and also that they got 50X runtime improvement in 2 months!

A Major Communication Company said that they can now automatically split at RTL entire chips in smaller hard macros using Defacto’s STAR. With Defacto solutions they accelerated a lot their custom tool development with multi development languages support!

If you missed one of the presentations below, just let us know by clicking on the following link:

  • Generating a Layout friendly RTL/Netlist by Defacto STAR
  • A Cost-effective RTL Partitioning Methodology for Large SoC Designs
  • Accelerate SoC Design Integration with STAR
  • Benefit from STAR as a Multi-Language APIs Design Platform
  • Bring RTL Signoff to the next level with STAR

- Defacto Team

EDA Senior Software Engineer

We are hiring !

Job Description:

As member of the Development team, you will develop and support Defacto RTL and Gate-level solutions. Your responsibilities as team member will include but not be limited to:

  • Participate in internal customer requirements collection,
  • Support and develop both existing and new solutions, 
  • Work with product and application engineers to harmonize/optimize the development environment and methodologies.


You must possess a Master degree or a PhD in Computer Science / Electrical Engineering with a minimum of 5 years of relevant experience in following areas: 

  • Software architecture (Object-Oriented) and development in EDA (Electronic Design Automation) 
  • C/C++, Tcl/Tk, CVS 
  • Linux OS
  • (Optional) VHDL, Verilog, SystemVerilog

The candidate must have excellent communication (oral/written) in French and in English, with very strong analytical skills. He/she must be self-directed, proactive and team-oriented.

Location: Grenoble, France 
Full/Part Time: Full Time 
Job Type: Experienced 
Regular/Temporary: Regular

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Defacto on EDA Café

Defacto at DAC: Top semiconductor companies are presenting at the Defacto booth how Defacto's STAR helps accelerating SoC design integration



Field Application Engineer (San Diego, CA)

We are hiring !

Job description

The successful candidate will provide technical support to users of  Defacto’s design solutions. He/she should be able to create and make persuasive technical presentations and conduct crisp, compelling demonstrations and benchmarks. Strong technical understanding of the product and the design environment will be critical.

Experience within a large semiconductor or an EDA company is a plus



  • Expertise in scripting: Tcl, Perl
  • Knowledge of digital circuit design: Verilog, VHDL
  • Knowledge of front-end tools: RTL synthesis, Design For Test, Simulation, Formal equivalence
  • Experience of EDA tools in the design flow of integrated circuits
  • Practice of UNIX / Linux, using C-shell
  • Minimum of 5 years experience
  • Your English is very good and professional
  • Self-reliance and work actively with members of the R & D team 

The candidate must have excellent communication (oral/written) in English.


Job location

  • San Diego CA, USA
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