Design Restructuring with STAR

Overview

Reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. Restructuring an SoC design by building multiple variants of the same SoC with different PPA scenarios, is often needed. STAR provides a complete and powerful automation platform to restructure complex SoCs at both RTL or gate-level.

 

Typical Cases

Tiling

 

  • Split the top level into smaller hard macros for concurrent synthesis / implementation
  • Group features expected to be in the same physical area, but not necessarily designed together
  • Quick re-arrangement of clusters (tiles) when floorplan changes

Power Aware Design Restructuring

  • Logical design hierarchy modification to meet power intent changes

Insertion of Custom Structures

  • Low power, DFX, etc.

 

Key Features

  • Unified API for design exploration and design editing
    • Same scripts can be executed both at RTL and netlist level
  • Complete RTL coverage: Verilog, VHDL, SystemVerilog and mixed language support
  • Preserved look and feel for generated RTL
  • Ability to generate custom reports about design changes
    • Added / removed ports, nets, instances
    • Clusters connectivity before/after design restructuring
  • Unified data model
    • Multi-format support: RTL, gate-level, IPXACT, UPF, SDC, LEF/DEF
    • Automatic power intent / synthesis constraints refinementPower aware design restructuring
  • Flexible insertion of feedthrough
  • Ability to clean/optimize logic for optimal synthesis

 

Benefits

  • Lower the burden on physical designers to reduce TAT (Turn Around Time)
  • Eliminate error-prone manual RTL code editing, generate “correct-by-construction” RTL
  • Reduce project development schedule by several men-months
    • Manual design restructuring can take weeks to several months for complex SoCs
    • With STAR, the same process can take just a few days, including the reviews
  • Unified naming convention for ECO phases
    • Avoid disturbance for physical design team
  • Accelerate overall design flow
  • Reduce die size and therefore cost, improve power consumption

 

"Design restructuring Explained" "Design Deconstruction"
Connection